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When a +5 volt gate signal is applied to the input it flows through a 10k resistor, charging
the .001 uf capacitor. This causes a voltage to appear briefly at the base of the 2n3904 transistor
which in turn causes a brief voltage drop at its collector. The 3904 collector is connected to
an input of a flip-flop formed by two NAND gates in the 4093 chip. The voltage drop causes the
flip-flop to set and its Q output to go high. The flip-flop Q output controls a 4066 switch which
closes when the output is high. This switch connects the gate signal (buffered and slightly amplified
by a TL084 opamp) through the Attack potentiometer and diode to the 1 or 10 uf capacitor. When the
switch closes, the capacitor begins charging at a rate determined by the 1 meg Attack pot. As
the capacitor charges, its voltage is monitored by a TL084 based comparator. When the cap voltage
exceeds 4.9 volts (as set by a 68k/47k voltage divider attached to the TL084 + input) the comparator
output goes low. The comparator output is connected to the flip-flop reset, which is triggered by
the low signal. The flip-flop thus resets and its Q output goes low while the ~Q output goes high.
When the Q output goes low, the switch it is connected to opens and the capacitor is no longer
able to charge through the Attack potentiometer. Instead the switch connected to the ~Q flip-flop
output closes and the capacitor begins discharging through the 1 meg Decay pot and diode until
it reaches the voltage set by the 100k Sustain pot (via an opamp buffer). The circuit remains in
this state until the gate signal drops to 0 volts, which causes the capacitor to drain through the
1 meg Release pot via the output of the gate opamp (which goes low with the gate signal).
The capacitor voltage is connected to a TL084 buffer. The output of this buffer serves as the
output of the circuit. An LED is also connected to the output buffer via a 2N3904 transistor.
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